Constant advances of semiconductor manufacturing technology have greatly shrunken the size of electronic elements but greatly improve their performances. Conventional semiconductor manufacturing processes mainly focus on shrinking the size of transistors to increase circuit density of elements so that element size can be reduced to improve switching speed and power consumption, thereby to enhance the functionality of the elements. Shrinking the element size must be incorporated with precisely controlled etching process and equipments to make improving production yield possible. Please refer to FIGS. 1A through 1D for a conventional technique with a substrate 1 pending to be etched as an example for discussion. The substrate 1 mainly is made of silicon and etched to form trenches filled with insulated material. A first trench 2 on the right side is filled with the insulated material via high density plasma (HDP) 3 and second trenches 4 on the left side are filled with spin-on dielectric (SOD) 5 as examples. Due to the insulated materials in the first trench 2 and second trenches 4 are different from the material of the substrate 1, they must be etched by stages via different etching solutions or etching plasma. Referring to FIG. 1B, first etch the insulated materials in the first trench 2 and second trenches 4, with a photo mask 11 placed above the first trench 2 so that a portion of HDP 3 is retained. Referring to FIG. 1C, etch the substrate 1 to form a ditch 6. Because of the formation of the first trench 2 and second trenches 4, the substrate 1 is etched laterally and downward by the plasma. Hence a sub-trench 7 is formed on the surface of the substrate 1 near the first trench 2 and a linear horn 8 is formed on the surface of the second trench 4. As a result, the bottom surface 9 of the ditch 6 is uneven. Referring to FIG. 1D, when a metal wire 10 is formed on the bottom surface 9, the uneven bottom surface 9 also causes the metal wire 10 to form an uneven bonding surface between them.
In the process of manufacturing transistor, separation of the metal wire 10 must be performed to form a gate. Please refer to FIG. 2A for a perspective view after the aforesaid etching processes have been finished, with one set of first trench 2 and one set of second trench 4 as an example, also revealing the ditch 6. Refer to FIG. 2B for the structure with one side of the ditch 6 cut away to show a connecting condition between the metal wire 10 and bottom surface 9. FIG. 2C illustrates separation of the metal wire 10. As the bonding surface is formed at the junction of the bottom surface 9 and metal wire 10, when cutting the metal wire 10 to the bottom surface 9 is desired, a fully separated section 12 is formed while a non-separated section 13 remains because of the uneven bonding surface. Hence parts of the left side and right side of the metal wire 10 are still connected and conductive, and a etching process has to be performed until the non-separated section 13 of the metal wire 10 is fully separated to expose the sub-trench 7 and fully separate the metal wire 10 as shown in FIG. 2D. But such a process also etches the left side and right side of the metal wire 10 to become thinner, thus the metal wire 10 could drop out or being damaged. In addition, the uneven surface resulted from the sub-trench 7 also creates stacking problem among different layers during fabrication to increase the risk of current leakage.